This invention relates to a process for reducing the lateral distance between elements formed at the same level in an integrated circuit such that the lateral distance is less than the minimum distance that may be attained using standard photolithographic processes.
The lateral separation distance between conductive or other elements at the same processing level, such as gates and wordlines, of integrated circuits when using conventional photolithographic process is generally limited to the minimum processing dimension permitted by the photolithographic process used. That is, if the minimum distance between photoresist strips deposited on a semiconductor strip is one-half micron, then the minimum distance between gates of adjacent memory cells, and/or between wordlines associated with adjacent rows of cells, is also one-half micron.
It is desirable to decrease the spacing between identical components of integrated circuits. For example, the capacity of a memory array on a microchip may be increased by decreasing the distance between identical elements of adjacent memory cells. It is also desirable in some applications to increase the capacitive coupling between conductive elements by increasing the size of those elements to the maximum possible dimension for a given cell size.